Syncronizing Timer0,Timer1, Timer2 PWM outputs


i can't seem synchronize 16-bit timer1 output 8-bit timer0 , timer2 outputs. want clarify able synchronize timer0 , timer2 each other timer1 proving difficult match.  feel missing something. here's setup() code:
code: [select]

gtccr = (1<<tsm)|(1<<psrasy)|(1<<psrsync); // halt timers
   
   // timer1 settings --------------------------------------------------
   tccr1a = 0; // reset timer 1 control register a
   tccr1b = 0; // reset timer 1 control register b
 
   tccr1a |= (1 << com1a1) | //
             (0 << com1a0) | // clear oc1a on compare match counting
             (1 << com1b1) | //
             (1 << com1b0) | // set oc1b on compare match counting
             (0 << wgm10)  |
             (1 << wgm11)  ;
   tccr1b |= (0 << wgm12)  |
             (0 << wgm13)  | // pwm phase freq correct, top=0x01ff, switching freq 15.63khz
             (1 << cs10)   ; // no prescalar
   
 
  // timer1 default dutycycle
     ocr1a = 0xff-deadtimecnt;
     ocr1b = 0xff+deadtimecnt;   
   
  // timer1 interrupt settings
  timsk1 = 0; // reset timer1 interrupt mask register
  timsk1 |= (1 << toie1) ;  // timer2 overflow interrupt tov1 bit set when tcn1=bottom 
 
   // timer 0 settings-------------------------------------------
   tccr0a = 0; // reset timer 0 control register a
   tccr0b = 0; // reset timer 0 control register b
   tccr0a |= (1 << com0a1); // phase correct pwm, com0a1=1, com0a0=0
   tccr0a |= (1 << com0b1); // phase correct pwm, com0b1=1, com0b0=1
   tccr0a |= (1 << com0b0);
   tccr0a |= (1 << wgm00); // phase correct pwm, top=0xff, wgm00=1, wgm01=0, wgm02=1, mode 1
   tccr0b |= (1 << cs00); // clk-i/o, no prescaling
   
   ocr0a = 0x7f-deadtimecnt;
   ocr0b = 0x7f+deadtimecnt;   
 
   
  // timer2 settings -------------------------------------------------------
  tccr2a = 0; // reset timer 2 control register a
  tccr2b = 0; // reset timer 2 control register b
 
  tccr2a |= (1 << com2a1) | //
            (0 << com2a0) | // clear oc2a on compare match counting
            (1 << com2b1) | //
            (1 << com2b0) | // set oc2b on compare match counting
            (1 << wgm20)  |
            (0 << wgm21)  ; // pwm phase correct, top=0xff, 31.37khz
  tccr2b |= (0 << wgm22)  |//
            (1 << cs20)   ; // no prescalar
 
   // timer2 default dutycycle
    ocr2a = 0x7f-deadtimecnt;
    ocr2b = 0x7f+deadtimecnt;   
     
  // timer2 interrupt settings
   timsk2 = 0; // reset timer2 interrupt mask register
   timsk2 |= (1 << toie2) ;  // timer2 overflow interrupt tov2 bit set when tcn2=bottom 
 
  // timer2 asynchronus status register
  assr = 0; // reset async status register, timer2 clk = cpu clk
 
      // set timers same value
  tcnt0 = 0x00; // set timer0 0
  tcnt1 = 0x0000; // set timer1 0
  tcnt2 = 0x00; // set timer2 0
 
  gtccr = 0;  // release timers

i figured out happening because number of clock cycles in 16 bit timer1 not exact multiple of clock cycles in timer0 or timer2.


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